As conventional CMOS transistors are scaled down, power dissipation due to off-state leakage current increases. In an effort to reduce this power consumption, tunneling field effect transistors (TFET) have been proposed because of the extremely low off-state leakage current capability. Additional technical background information regarding TFETs may be found in “Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec,” Choi, W. Y., et al., IEEE Electron Device Letters, Vol. 28, No. 8, August 2007; “Double-Gate Strained-Ge Heterostructure Tunneling FET (FTET) With Record High Drive Currents and <60 mV/dec Subthreshold Slope,” Krishnamohan, Tejas, et al., IEEE 2008; “Impact of SOI, Si1-xGexOI and GeOI Substrates On CMOS Compatible Tunnel FET Performance,” Mayer, F., et al., IEEE 2008; and “Green Transistor—A VDD Scaling Path For Future Low Power ICs,” Hu, Chenming, et al., IEEE 2008, which are incorporated herein by reference.
Referring to FIG. 1A, there is shown a conventional TFET. Instead of both source and drain regions having the same conductivity type (e.g., P-type or N-type) as done in conventional MOSFETs, the TFET is constructed to include a P+ type drain/source and N+ type source/drain in a substrate. As will be appreciated, a conventional TFET may act as either a p-channel or n-channel depending on the gate voltage value.
Referring to FIGS. 1B and 1C, in the OFF-state, the gage bias voltage (Vgs) is zero with insufficient band bending to allow tunneling. In this state, the leakage current is extremely low and is due to the drift of minority carriers (similar to that of a reverse biased P-I-N diode). In the ON-state (usually with the P+ source grounded and the N+ drain at a fixed positive bias), the gate induces sufficient band bending resulting in a reduction of the tunneling barrier width to less than 5 nanometers (nm). This leads to substantial band-to-band tunneling of electrons from the valence band of the P+ source region to the conduction band of the N+ drain region.
Advantages of conventional TFETs include a sub-60 mV subthreshold slope, low off-state leakage current, control of short channel effects, and an intrinsic channel that minimizes any dopant fluctuation issues. In contrast, the main disadvantage of conventional TFETs is the low drive current because the current originates from band-to-band tunneling. In other words, the drive current (drain current Id) capability of conventional TFETs is much lower than conventional MOSFETs. FIG. 2 illustrates a general comparison of the Id-Vg curves between a conventional TFET and conventional MOSFET.
To increase the drive current, it has been proposed to utilize silicon-germanium (SiGe) in the source region near the tunneling region. FIGS. 3A, 3B and 3C illustrate the typical tunneling width for silicon and SiGe in the source region. As shown in FIG. 3B, the increase in the valence bandgap (Ev) resulting from a SiGe source region decreases/narrows the tunneling barrier width. However, because conventional SiGe processes usually result in a gap or space between the SiGe source region and the gate stack due to an offset spacer, the tunneling barrier width is still determined by the valance bandgap of silicon (in the channel). Inclusion of the spacer gap causes an increase (shown as LH) in the tunnel barrier width—effectively negating most of the benefits gained by utilizing SiGe in the source region.
Accordingly, there is a need for an improved TFET structure (and method of fabricating) having increased drive current capabilities.